Modular-logarithmic Co-processor for Massive Arithmetic Calculations
DOI:
https://doi.org/10.14529/cmse170202Keywords:
residue number system, logarithmic number system, reconfigurable architecture, highly reliable computingAbstract
The paper presents a conceptual design of an IP module of mathematical coprocessor. It consists of a set of processing cores of the same kind which perform single-cycle scalar, or vector operations with real numbers. The processed data is represented in the modular logarithmic format that provides two levels of translating the original numbers, namely: the modular level instead of the conventional positional system and the logarithmic level instead of the floating point format. As a result of the research and development, new scientific and technical solutions are proposed that implement the proposed methods of computing and coding data. Owing to this feature a coprocessor has a higher performance, a higher accuracy and a higher level of reliability, as compared to the known analogs. Convert codes in modular-logarithmic number system and vice versa does not introduce significant time delays in a large stream of input data by offering hardware solutions pipelined process of interpolation of the logarithm function and conversion of residual classes system codes. A prototype coprocessor is an FPGA-based IP module. Companies developing general-purpose processors are the target market for this design.References
Top 10 Sites for November 2016. Available at: www.top500.org/lists/2016/11 (accessed: 26.01.2017).
-2008 – IEEE Stander for floating-Point Arithmetic. Revision of ANSI/IEEE Std 754-1985. Available at: ieeexplore.ieee.org, 2008 (accessed: 26.01.2017).
Osinin I.P. Vysokonadezhnyy modulyarno-logarifmicheskiy protsessor s rekonfiguriruemoy arkhitekturoy. [The highly-modular logarithmic processor with a reconfigurable architecture]. Parallelnye vychislitelnye tekhnologii (PaVT'2016): Trudy mezhdunarodnoj nauchnoj konferentsii (Arkhangel'sk, 28 marta – 1 aprelya 2016). [Parallel Computational Technologies (PCT'2016): Proceedings of the International Scientific Conference (Arkhangelsk, Russia, March, 28 – April, 1, 2016)]. Chelyabinsk, Publishing of the South Ural State University, 2016. P. 642-654.
Osinin I.P., Knyaz'kov V.S. Napravleniya razvitiya arkhitektury rekonfiguriruemykh vychislitel'nykh platform. [Directions of development of architecture of reconfigurable computing platforms]. Matematicheskoe modelirovanie razvivayushcheysya ekonomiki,
ekologii i tekhnologiy (EKOMOD-2016): Trudy IX Vserossiyskoy nauchnoy konferentsii (Kirov, 4-9 iyulya 2016). [Mathematical modeling of a developing economy, ecology and technology (ECOMOD-2016): Proceedings of the Scientific Conference (Kirov, Russia, July, 4 – July, 9, 2016)]. Kirov: Publishing of the Vyatka State University, 2016. P. 486495.
Coleman J.N., Chester E.I. Arithmetic on the European Logarithmic Microprocessor // IEEE Transactions on Computers. 2000. Vol. 49, No. 7. P. 702–715.
Ismail R.C., Hussin R., Muzad S.A. Interpolator Algorithms for approximating the LNS addition and substraction // IEEE International Conference on Circuits and Systems (ICCAS). Kaula Lumpur, 3-4 Oct. 2012. P. 174–179.
Chervyakov N.I. Modulyarnye parallel'nye vychislitel'nye struktury neyroprotsessornykh sistem [Modular structure of the parallel computing systems neuroprocessor]. Moscow: Publishing Fizmatlit, 2003. 288 p.
Omondi A. Residue Number System:Theory and Implementation. London: Imperial College Press, 2007. 312 p.
Kalmykov I.A. Teoriticheskie osnovy vychisleniy v polinomial'noy sisteme klassov vychetov, orientirovannykh na postroenie otkazoustoychivykh system. [Theoretically bases of calculations in polynomial system of residue classes, focused on building a faulttolerant systems]. Stavropol: Publishing North-Caucasian Federal University, 2006. 347 p.
